Semiconductor structure and method for forming the same
US11139011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Sep 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.