High resistivity semiconductor-on-insulator wafer and a method of manufacturing
US11139198B2 · kind B2 · utility
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26References
32Claims
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Key dates
| Filing date | Dec 28, 2018 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Feb 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.