Integrated circuit device with crenellated metal trace layout

US11139241B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Patrick Morrow · Portland, US
• Mauro J. Kobrinsky · Portland, US
• Mark Bohr · Beaverton, US
• Tahir Ghani · Portland, US
• Rishabh Mehandru · Portland, US
• Ranjith Kumar · Beaverton, US

Key dates

• Filing date: Dec 7, 2016
• Grant date: Oct 5, 2021
• Expiry date: Dec 7, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.