Three-dimensional memory arrays with layer selector transistors
US11139300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2019 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Nov 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6755
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.