Efficiency for coordinated start interpretive execution exit for a multithreaded processor

US11150905B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jonathan D. Bradbury · Poughkeepsie, US
• Fadi Y. Busaba · Poughkeepsie, US
• Mark S. Farrell · Pleasant Valley, US
• Charles W. Gainey, Jr. · Poughkeepsie, US
• Dan F. Greiner · San Jose, US
• Lisa C. Heller · Rhinebeck, US
• Jeffrey P. Kubala · Poughquag, US
• Damian L. Osisek · Vestal, US
• Donald W. Schmidt · Stone Ridge, US
• Timothy Siegel · Staatsburg, US

Key dates

• Filing date: Sep 27, 2017
• Grant date: Oct 19, 2021
• Expiry date: Aug 18, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/522
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.