Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device
US11152214B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Apr 20, 2016 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Jul 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.