3D integrated ultra high-bandwidth multi-stacked memory
US11152343B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2019 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.