Inventor · Portland, OR, US

Amrita Mathuriya

260Patents
12h-index
48Co-inventors
78Inventor score

Filing activity: Sep 25, 2018 → Dec 11, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US11482270B1 Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic Electricity 62 Active
US10944404B1 Low power ferroelectric based majority logic gate adder Electricity 53 Active
US11139270B2 Artificial intelligence processor with three-dimensional stacked memory Emerging Cross-Sectional Technologies 46 Active
US11043472B1 3D integrated ultra high-bandwidth memory Emerging Cross-Sectional Technologies 46 Active
US11423967B1 Stacked ferroelectric non-planar capacitors in a memory bit-cell Electricity 29 Active
US11165430B1 Majority logic gate based sequential circuit Electricity 26 Active
US11152343B1 3D integrated ultra high-bandwidth multi-stacked memory Emerging Cross-Sectional Technologies 25 Active
US11171115B2 Artificial intelligence processor with three-dimensional stacked memory Emerging Cross-Sectional Technologies 22 Active
US11694940B1 3D stack of accelerator die and multi-core processor die Emerging Cross-Sectional Technologies 21 Active
US11277137B1 Majority logic gate with non-linear input capacitors Electricity 19 Active
US10951213B1 Majority logic gate fabrication Electricity 17 Active
US10642922B2 Binary, ternary and bit serial compute-in-memory circuits Physics 15 Active
US11283453B2 Low power ferroelectric based majority logic gate carry propagate and serial adder Electricity 11 Active
US11501813B1 Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell Electricity 11 Active
US11521667B1 Stacked ferroelectric planar capacitors in a memory bit-cell Electricity 11 Active
US11538514B1 Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell Electricity 10 Active
US11545204B1 Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels Electricity 10 Active
US11418197B1 Majority logic gate having paraelectric input capacitors and a local conditioning mechanism Electricity 10 Active
US11048434B2 Compute in memory circuits with time-to-digital computation Physics 9 Active
US11025254B1 Linear input and non-linear output threshold logic gate Electricity 9 Active
US11303280B1 Ferroelectric or paraelectric based sequential circuit Emerging Cross-Sectional Technologies 9 Active
US10860682B2 Binary, ternary and bit serial compute-in-memory circuits Physics 8 Active
US11374575B1 Majority logic gate with non-linear input capacitors and conditioning logic Electricity 8 Active
US10748603B2 In-memory multiply and accumulate with global charge-sharing Physics 7 Active
US11061646B2 Compute in memory circuits with multi-Vdd arrays and/or analog multipliers Physics 7 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.