Self-aligned isolation for nanosheet transistor
US11152464B1 · kind B1 · utility
0Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2020 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Mar 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having self-aligned isolations. In a non-limiting embodiment of the invention, a first gate stack is formed over channel regions of a first nanosheet stack. A second gate stack is formed over channel regions of a second nanosheet stack adjacent to the first nanosheet stack. An isolation pillar is positioned between the first gate stack and the second gate stack. The isolation pillar includes a top portion having a first width and a bottom portion having a second width less than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.