Multi-chip package structures with discrete redistribution layers
US11164817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Nov 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.