Channel layer formed in an art trench

US11164974B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Willy Rachmady · Beaverton, US
• Matthew V. Metz · Portland, US
• Gilbert Dewey · Beaverton, US
• Nancy Zelick · Portland, US
• Harold W. Kennel · Portland, US
• Nicholas G. Minutillo · Beaverton, US
• Cheng-Ying Huang

Key dates

• Filing date: Sep 29, 2017
• Grant date: Nov 2, 2021
• Expiry date: Oct 16, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.