Memory system with dynamic calibration using a trim management mechanism
US11177006B2 · kind B2 · utility
5Cited by
8References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 28, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Jan 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: calibrate read levels based on associated read results, wherein the read levels are tracked via optimization target data that at least initially includes at least one read level in addition to a target trim; and remove a calibrated read level from the optimization target data when the calibrated read level satisfies a calibration condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.