Formation of termination structures in stacked memory arrays

US11177279B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Matthew J. King · Boise, US
• Anilkumar Chandolu · Boise, US
• Indra V. Chary · Boise, US
• Darwin A. Clampitt · Boise, US
• Gordon A. Haller · Boise, US
• Thomas George · Clinton, US
• Brett D. Lowe · Boise, US
• David Daycock · Boise, US

Key dates

• Filing date: May 18, 2020
• Grant date: Nov 16, 2021
• Expiry date: May 18, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/40

Abstract

In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.