Patent · US Active

Semiconductor arrangement, laminated semiconductor arrangement and method for fabricating a semiconductor arrangement

US11183445B2 · kind B2 · utility

0Cited by

4References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dirk Ahlers · Hersbruck, DE
Frank Daeche · Unterhaching, DE
Daniel Schleisser · Munich, DE
Thomas Stoek · Buxtehude, DE

Key dates

Filing date	Jan 29, 2020
Grant date	Nov 23, 2021
Priority date	—
Expiry date	Mar 13, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/92244
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.