Dynamic control of quasi-cyclic low-density parity-check bit-flipping decoder
US11190212B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Jul 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1137
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Devices, systems, and methods for dynamic control of a quasi-cyclic low-density parity-check (QC-LDPC) bit-flipping decoder are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from an irregular QC-LDPC code, performing a plurality of decoding iterations on the received noisy codeword, each of the plurality of decoding iterations comprising processing of N circulant matrices, performing, before processing a current circulant matrix in a current M-th iteration of the plurality of decoding iterations, operations that include computing a number of bit flips that have occurred over the processing of N previous circulant matrices, the N previous circulant matrices spanning the current M-th iteration and an (M−1)-th iteration, wherein M and N are positive integers, and wherein M≥2, and updating, based on the number of bit flips, a bit-flipping threshold, and processing, based on the updated bit-flipping threshold, the current circulant matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.