Bit-flipping decoder architecture for irregular quasi-cyclic low-density parity-check codes
US11206043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Apr 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.