Patent · US Active

Parallelized rounding for decimal floating point to binary coded decimal conversion

US11210064B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Stefan Payer · Stuttgart, DE
Silvia M. Mueller · Altdorf, DE
Nicol Hofmann · Stuttgart, DE
Razvan Peter Figuli · Remchingen, DE

Key dates

Filing date	Jul 30, 2019
Grant date	Dec 28, 2021
Priority date	—
Expiry date	Mar 22, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03M7/24
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.