Vertical field effect transistor with bottom spacer

US11217692B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Christopher J. Waskiewicz · Rexford, US
• Ruilong Xie · Niskayuna, US
• Jay William Strane · Wappingers Falls, US
• Hemanth Jagannathan · Niskayuna, US

Key dates

• Filing date: Jan 9, 2020
• Grant date: Jan 4, 2022
• Expiry date: Feb 27, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/518

Abstract

A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.