Patent · US Active

Parallel rounding for conversion from binary floating point to binary coded decimal

US11221826B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Stefan Payer · Stuttgart, DE
Silvia M. Mueller · Altdorf, DE
Razvan Peter Figuli · Remchingen, DE
Revital Arieli · Nes Ziona, IL

Key dates

Filing date	Jul 30, 2019
Grant date	Jan 11, 2022
Priority date	—
Expiry date	Apr 1, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03M7/24
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.