Low dimensional material device and method
US11244866B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2020 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Jul 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/882
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.