Memory arrays and methods used in forming a memory array comprising strings of memory cells
US11244955B2 · kind B2 · utility
0Cited by
10References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 25, 2019 |
| Grant date | Feb 8, 2022 |
| Priority date | — |
| Expiry date | Aug 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.