Superjunction transistor arrangement and method of producing thereof

US11245002B2 · kind B2 · utility

Assignee

• Infineon Technologies Dresden GmbH & Co. KG · DE

Inventors

• Rolf Weis · Dresden, DE
• Henning Feick · Dresden, DE
• Franz Hirler · Isen, DE
• Andreas Meiser · Unterhaching, DE

Key dates

• Filing date: Dec 21, 2018
• Grant date: Feb 8, 2022
• Expiry date: Dec 21, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/411

Abstract

A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer.