Compute near memory with backend memory
US11251186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Mar 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.