Gate fringing effect based channel formation for semiconductor device

US11251189B2 · kind B2 · utility

Assignee

• LONGITUDE FLASH MEMORY SOLUTIONS LTD. · IE

Inventors

• Youseok Suh · Cupertino, US
• Sung-Yong Chung · Davis, US
• Ya-Fen Lin · Saratoga, US
• Yi-Ching Wu · Hengshan, TW

Key dates

• Filing date: Apr 10, 2019
• Grant date: Feb 15, 2022
• Expiry date: Apr 10, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.