Distributed semiconductor die and package architecture
US11257804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Jun 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1432
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.