Three-dimensional nanoribbon-based dynamic random-access memory
US11257822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2019 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Nov 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.