Defect classification and source analysis for semiconductor equipment
US11263737B2 · kind B2 · utility
4Cited by
5References
40Claims
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Key dates
| Filing date | Jan 10, 2019 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Defects on a substrate comprising electronic components can be classified with a computational defect analysis system that may be implemented in multiple stages. For example, a first stage classification engine may process metrology data to produce an initial classification of defects. A second stage classification engine may use the initial classification, along with manufacturing information and/or prior defect knowledge to output probabilities that the defects are caused by one or more potential sources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.