Bonding pads including interfacial electromigration barrier layers and methods of making the same
US11270963B2 · kind B2 · utility
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16References
20Claims
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Key dates
| Filing date | Jan 14, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jan 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.