Semiconductor device power metallization layer with stress-relieving heat sink structure
US11276624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Mar 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/4871
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.