Data processing engine array architecture with memory tiles

US11296707B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Javier Cabezas Rodriguez · Campbell, US
• Juan J. Noguera Serra · San Jose, US
• David Clarke · Dublin, IE
• Sneha Bhalchandra Date · Santa Clara, US
• Tim Tuan · San Jose, US
• Peter McColgan · Dublin, IE
• Jan Langer · Chemnitz, DE
• Baris Ozgul · Dublin, IE

Key dates

• Filing date: Mar 9, 2021
• Grant date: Apr 5, 2022
• Expiry date: Mar 9, 2041

Classification

• Technology area (CPC —): General

Abstract

An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.