Method of fabricating semiconductor device including dummy via anchored to dummy metal layer
US11302654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Sep 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/33519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.