Ferroelectric or paraelectric based sequential circuit
US11303280B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2021 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Aug 19, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.