Floating body DRAM with reduced access energy
US11309015B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.