Semiconductor package including stacked semiconductor chips
US11309303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2021 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.