Integrated CMOS source drain formation with advanced control

US11309404B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Benjamin Colombeau · San Jose, US
• Tushar Mandrekar · Santa Clara, US
• Patricia M. Liu · Saratoga, US
• Suketu Arun Parikh · San Jose, US
• Matthias Bauer · Phoenix, US
• Dimitri Kioussis · San Jose, US
• Sanjay Natarajan · Portland, US
• Abhishek Dube · Fishkill, US

Key dates

• Filing date: Jul 3, 2019
• Grant date: Apr 19, 2022
• Expiry date: Aug 31, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.