Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same
US11315635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2021 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jan 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.