Multiple spacer patterning schemes

US11315787B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Tzu-shun Yang · Milpitas, US
• Rui Cheng · San Jose, US
• Karthik Janakiraman · San Jose, US
• Zubin Huang · Santa Clara, US
• Diwakar Kedlaya · San Jose, US
• Meenakshi GUPTA · San Jose, US
• Srinivas Guggilla · San Jose, US
• Yung-Chen Lin · Los Angeles, US
• Hidetaka Oshio · Tokyo, JP
• Chao-Sung Li · Santa Clara, US
• Gene Lee · San Jose, US

Key dates

• Filing date: Mar 17, 2020
• Grant date: Apr 26, 2022
• Expiry date: Mar 17, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76816
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.