Electronic package and manufacturing method thereof
US11315881B1 · kind B1 · utility
3Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Dec 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.