Semiconductor structure with buried power line and buried signal line and method for manufacturing the same
US11315928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Sep 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate having a first top surface. An active region is surrounded by an isolation region in the substrate. A buried power line and a buried signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first top surface of the substrate to cover the buried power line and the buried signal line. A second circuit layer is disposed on the first top surface of the substrate and separated from the first circuit layer. A cell capacitor is disposed on and electrically coupled to the first circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.