Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same
US11316024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2021 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Feb 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.