Nitride-based transistors with a protective layer and a low-damage recess

US11316028B2 · kind B2 · utility

Assignee

• Wolfspeed, Inc. · US

Inventors

• Scott Sheppard · Chapel Hill, US
• Richard Peter Smith · Carrboro, US
• Zoltan Ring · Chapel Hill, US

Key dates

• Filing date: Feb 7, 2011
• Grant date: Apr 26, 2022
• Expiry date: Feb 7, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.