Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks
US11322507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2021 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Feb 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes recessing the upper surface of first and second areas of a semiconductor substrate relative to the third area of the substrate, forming a pair of stack structures in the first area each having a control gate over a floating gate, forming a first source region in the substrate between the pair of stack structures, forming an erase gate over the first source region, forming a block of dummy material in the third area, forming select gates adjacent the stack structures, forming high voltage gates in the second area, forming a first blocking layer over at least a portion of one of the high voltage gates, forming silicide on a top surface of the high voltage gates which are not underneath the first blocking layer, and replacing the block of dummy material with a block of metal material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.