Managing sub-block erase operations in a memory sub-system
US11335412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Nov 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.