Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US11335563B2 · kind B2 · utility
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Key dates
| Filing date | Mar 2, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Mar 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.