Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations
US11347477B2 · kind B2 · utility
1Cited by
2References
21Claims
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Key dates
| Filing date | Sep 27, 2019 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jan 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a number (X) of multiply-accumulate (MAC) circuits that are dynamically configurable. The MAC circuits can either compute an output based on computations of X elements of the input vector with the weight vector, or to compute the output based on computations of a single element of the input vector with the weight vector, with each element having a one bit or multibit length. A first memory can hold the input vector having a width of X elements and a second memory can store the weight vector. The MAC circuits include a MAC array on chip with the first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.