Electrical fuse formation during a multiple patterning process

US11348870B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Jiehui Shu · Clifton Park, US
• Xiaoqiang Zhang · Rexford, US
• Haizhou Yin · Poughkeepsie, US
• Moosung Chae · Poughkeepsie, US
• Jinping Liu · Ballston Lake, US
• Hui Zang · Guilderland, US

Key dates

• Filing date: Jul 1, 2020
• Grant date: May 31, 2022
• Expiry date: Sep 8, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/5256
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.