Semiconductor material having tunable permittivity and tunable thermal conductivity
US11355340B2 · kind B2 · utility
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9References
28Claims
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Key dates
| Filing date | Jan 14, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Jan 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A layered structure for semiconductor application is described herein. The layered structure includes a starting material and a fully depleted porous layer formed over the starting material with high resistivity. In some embodiments, the layered structure further includes epitaxial layer grown over the fully depleted porous layer. Additionally, a process of making the layered structure including forming the fully depleted porous layer and epitaxial layer grown over the porous layer is described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.