Semiconductor device structures with liners
US11355607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.