Vertical field effect transistor with bottom source-drain region
US11355633B2 · kind B2 · utility
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12References
6Claims
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Key dates
| Filing date | Jan 3, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Jan 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.