FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling

US11362100B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Feng Zhou · Ann Arbor, US
• Xian Liu · Sunnyvale, US
• Steven Lemke · Boulder Creek, US
• Hieu Van Tran · San Jose, US
• Nhan Do · Saratoga, US

Key dates

• Filing date: Oct 13, 2020
• Grant date: Jun 14, 2022
• Expiry date: Jan 13, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6892

Abstract

Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.